1. Field of the Invention
The present invention relates generally to a method of fabricating a semiconductor device and more particularly, to a method of forming a contact with reduced contact resistance by employing a silicide layer in the fabrication of the semiconductor device.
2. Description of the Prior Art
Recent attempts to improve the characteristics of semiconductor devices are directed to reducing contact resistance and surface resistance in the source/drain regions of CMOS. Silicide compounds, with titanium, cobalt or nickel constituents, are under consideration as materials having low resistivity and low contact resistance.
Such materials with low resistivity and low contact resistance also have the ability to selectively form a silicide layer on the source/drain regions only. A related process in the art is often called a self-aligned silicide process.
In general, the silicide process is performed as follows. A thin metal layer is deposited and then turned into a silicide layer having an intermediate phase via a first heat treatment. Next, the silicide layer is subjected to a selective wet etching, so that silicide material remains on the source/drain regions only. Subsequently, by carrying out a second heat treatment, the desired silicide thin layer is obtained.
Permitting a reduction in contact resistance between silicon and metal, the silicide process is mainly applied to high efficiency logic semiconductor devices. Contrary to that, since highly-integrated memory semiconductor devices can be utilized even with a relatively higher contact resistance, the typical silicide process is not applied thereto without alterations.
That is, instead of the typical silicide process allowing a selective formation of the silicide layer over all portions of the source/drain region, a selective etching process after silicidation is used to obtain a final form of the silicide layer. Silicidation as herein used is the process of depositing a silicide layer on a substrate or other feature of a semiconductor device.
Thus, the resultant silicide layer remains on certain portions only of the source/drain region, occupying a smaller area in comparison with the case of using the typical process. Therefore, the silicide layer in the memory devices cannot avoid some increases of contact resistance.
One silicide material that is often used is titanium silicide. The titanium silicide, for example, TiSi2 with a C54 phase, has excellent properties, such as a low resistivity under 20 xcexcxcexa9xc2x7cm, and a good thermal stability. The titanium silicide is formed with an intermediate phase of C49 having a relatively higher resistivity of between 60 and 90 xcexcxcexa9xc2x7cm at a heat treatment temperature under 650xc2x0 C., and shifted in phase to a phase of C54 having a low resistivity at a temperature of between 700 and 900xc2x0 C.
However, it is difficult to shift titanium silicide to the C54 phase in design requirements where the silicide layer is less than 0.25 microns. The reason is that a nucleation site of the C54 phase can not be secured in a narrow line or pattern. This peculiar feature is designated as line width effect.
In order to overcome the line width effect, new ways such as pre-amorphization implant (PAI) and addition of molybdenum as an impurity have been studied by those of skill in the art.
On the other hand, increasing complexity of integrated circuits results in increasing reduction of the line width of a device circuit. Necessarily, the area of the source/drain region is consequently rapidly decreased.
In relation to the above, a conventional method for fabricating a semiconductor device is described hereinafter with reference to FIGS. 1 to 3.
As shown in FIG. 1, a trench isolation layer 3 is formed in a portion of a semiconductor substrate 1 to define an active region and a device isolation region.
Next, an insulating layer for a gate oxide layer 5, a polysilicon layer for a gate electrode 7, and an oxide layer for a capping layer 9 are sequentially deposited on the active region of the semiconductor substrate 1, and then selectively patterned to form the gate oxide layer 5, the gate electrode 7 and the capping layer 9, as shown.
Thereafter, a gate spacer 11 is formed on the lateral sides of the gate oxide layer 5, the gate electrode 7 and the capping layer 9. By implanting appropriate impurities, a source and drain region 13 is formed in the semiconductor substrate 1 under each gate spacer 11. Here, before the gate spacer 11 is formed, a lightly doped impurity region is additionally formed in the semiconductor substrate 1.
Then, a diffusion barrier layer 15 is deposited over an entire resultant structure, and an interlayer dielectric layer 17 is deposited on the diffusion barrier layer 15.
Subsequently, the interlayer dielectric layer 17 and the diffusion barrier layer 15 are selectively removed to form a contact hole 19 exposing the source and drain regions 13. During the removal of the interlayer dielectric layer 17 and the diffusion barrier layer 15, the source and drain regions 13 in the semiconductor substrate 1 are overetched to a certain predetermined depth.
Next, as shown in FIG. 2, a titanium layer 21 is formed on the interlayer dielectric layer 17 including over all surfaces of the contact hole 19. A titanium nitride layer 23, serving as a buffer layer, is then formed over the titanium layer 21.
Thereafter, a heat treatment process is performed for silicidation. Referring to FIG. 3, a silicide layer 25 is formed on the source and drain regions 13 by means of silicidation between the titanium layer 21 in the overetched portion and an upper part of the source and drain regions 13.
The above-described conventional method has a drawback, which is described below. As the area of the source/drain region is decreased, the area of the silicide layer actually formed is accordingly also decreased. In addition, the reduction in area of the silicide layer gives rise to the increase of contact resistance during subsequent heat treatment processes.
It is therefore an object of the present invention to provide a method of fabricating a semiconductor device with reduced contact resistance, thus preventing a rapid increase of contact resistance by enlarging the actual area of a silicide layer.
This and other objects in accordance with the present invention are attained by a method for fabricating a semiconductor device, the method comprising the steps of providing a silicon substrate; forming an isolation layer in the silicon substrate to define an active region and a device isolation region; forming a junction region in the active region of the silicon substrate; forming an interlayer dielectric layer on the silicon substrate; forming a contact hole exposing the junction region by selectively removing the interlayer dielectric layer; selectively removing an exposed portion of the junction region under the contact hole; sequentially forming a metal thin layer and a buffer layer on a resultant structure including a selectively removed portion of the junction region; and forming a silicide layer in the selectively removed portion of the junction region by performing a heat treatment.
According to another aspect of the present invention, the present invention provides a method for fabricating a semiconductor device, comprising the steps of providing a silicon substrate; forming an isolation layer in the silicon substrate to define an active region and a device isolation region; sequentially forming a gate oxide layer and a gate electrode on the active region of the silicon substrate; forming a junction region in the silicon substrate under each lateral side of the gate electrode; sequentially forming an oxide layer and a nitride layer on the silicon substrate; forming a contact hole exposing the junction region by selectively removing the oxide layer and the nitride layer; selectively removing an exposed portion of the junction region under the contact hole in vertical and/or lateral directions by means of a wet etching or a dry etching; sequentially forming a metal thin layer and a buffer layer on a resultant structure including a selectively removed portion of the junction region; and allowing silicidation between the metal thin layer formed in the selectively removed portion of the junction region and an upper part of the junction region by performing a rapid thermal annealing.